<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="6.x">Drupal-Biblio</source-app><ref-type>17</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Ou, N.</style></author><author><style face="normal" font="default" size="100%">Farahmand, T.</style></author><author><style face="normal" font="default" size="100%">Kuo, A.</style></author><author><style face="normal" font="default" size="100%">Tabatabaei, S.</style></author><author><style face="normal" font="default" size="100%">Ivanov, A.</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">Jitter models for the design and test of Gbps-speed serial interconnects</style></title><secondary-title><style face="normal" font="default" size="100%">Design Test of Computers, IEEE</style></secondary-title></titles><keywords><keyword><style  face="normal" font="default" size="100%">bit error rate</style></keyword><keyword><style  face="normal" font="default" size="100%">communication link performance</style></keyword><keyword><style  face="normal" font="default" size="100%">error statistics</style></keyword><keyword><style  face="normal" font="default" size="100%">high-speed interconnects</style></keyword><keyword><style  face="normal" font="default" size="100%">jitter</style></keyword><keyword><style  face="normal" font="default" size="100%">jitter model analysis</style></keyword><keyword><style  face="normal" font="default" size="100%">logic design</style></keyword><keyword><style  face="normal" font="default" size="100%">logic testing</style></keyword><keyword><style  face="normal" font="default" size="100%">parallel bus architectures</style></keyword><keyword><style  face="normal" font="default" size="100%">serial I/O interconnects</style></keyword><keyword><style  face="normal" font="default" size="100%">signal amplitude noise</style></keyword></keywords><dates><year><style  face="normal" font="default" size="100%">2004</style></year><pub-dates><date><style  face="normal" font="default" size="100%">jul.</style></date></pub-dates></dates><urls><web-urls><url><style face="normal" font="default" size="100%">http://dx.doi.org/10.1109/MDT.2004.34</style></url></web-urls></urls><number><style face="normal" font="default" size="100%">4</style></number><volume><style face="normal" font="default" size="100%">21</style></volume><pages><style face="normal" font="default" size="100%">302 - 313</style></pages><language><style face="normal" font="default" size="100%">eng</style></language><abstract><style face="normal" font="default" size="100%">We present a comprehensive analysis of jitter causes and types, and develops accurate jitter models for design and test of high-speed interconnects. The recent deployment of gigabit-per-second (Gbps) serial I/O interconnects aims at overcoming data transfer bottlenecks resulting from the limited ability to increase chip pin counts in parallel bus architectures. The traditional measure of a communication link's performance has been its associated bit error rate (BER), which is the ratio of the number of bits received in error to the total number of bits transmitted. When data rates increase, jitter magnitude and signal amplitude noise must decrease to maintain the same BER. As data rates exceed 1 Gbps, a slight increase in jitter or amplitude noise has a far greater effect on the BER.</style></abstract></record></records></xml>