Active Silicon Photonics Design

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3 Credits

ELEC 581

Course Structure/Operation
This is a one semester, project-based course. Students propose, model, design, and layout a Photonic Integrated Circuit (PIC) using active silicon photonics technology. The layout is designed based on the fabrication technology available from IME Singapore, providing students with an opportunity to design into an advanced photonics manufacturing process. Fabrication is available, at additional cost, via CMC Microsystems.

Prerequisites: At least one course at the graduate level on optics, waveguides, or lasers (e.g. EECE 584, 594), which involves the design, fabrication and testing of a photonic integrated circuit, or approval from the instructor.

Learning Objectives
By the end of the course, it is expected that students will be able to:

  • Model a nanophotonic device or circuit, both analytically and numerically
  • Design a photonic device or circuit, including necessary test structures
  • Create a mask layout of a photonic device or circuit
  • Write a report on a photonic device or circuit.

Detailed Course Outline

  • Overview: Silicon photonics enables the nanofabrication of optical components for optical communications, sensors, and biomedical devices. Example components include photonic crystals, waveguides (photonic crystal or ridge), gratings for fiber coupling, multiplexers (diffraction or arrayed waveguide), ring resonators, filters, modulators and germanium detectors.
  • Software design tools will be used for the modelling and design of the nanophotonic devices. Tools include numerical mathematical modelling (e.g. Matlab), optical simulation (e.g. Finite Difference Time Domain, Beam Propagation Method), electrical simulation (e.g. Comsol or Lumerical Device, mask layout (e.g. Mentor Graphics)
  • Experimental methodology. Optical fiber coupling, tunable lasers, detectors, polarization maintaining fibers and polarization control, spectrum measurements, temperature control, stability

Lectures (default lecture is 1 hour; topics spanning multiple hours noted)

  • The Foundry Model of Silicon Photonics
  • Fabrication process IME
  • SiEPIC Process Design Kit, Library, Linux Access
  • Mask Layout Tutorial - 3 hours
  • Design rules and DRC, Tiling, density rules, GDS
  • SiEPIC Library PCell Components and Mask Layout
  • Process simulation, using Sentaurus Process
  • PN junction modelling using Lumerical DEVICE / MODE
  • PN junction analytic model using Matlab
  • Lumped element MZI modeling using Lumerical INTERCONNECT
  • Travelling Wave Modulator - 3 hours
  • Microwave modelling, Sonnet; Coplanar strip waveguides (CPS), coplanar waveguide (GSG); impedance and group velocity; SParameters - 2 hours
  • Travelling wave MZI modeling using Lumerical INTERCONNECT
  • Microring modulator - 2 hours
  • Modelling ring modulator modeling using Lumerical INTERCONNECT
  • Detectors, germanium, superconductors - 2 hours
  • Modeling detectors using Lumerical FDTD / DEVICE - 2 hours
  • Schematic Driven Layout and System Modelling, Pyxis-INTERCONNECT integration - 3 hours
  • Tuning and switching using carrier injection PIN diodes and heaters
  • Design for Test
  • How to do design reviews
  • Case-study; Example layouts, reviewed by students

Texts and Bibliography
There is no required text for the course. Notes and additional readings (journal papers, theses) will be provided electronically.
Independent study: literature review on student’s chosen topic
Some additional information sources are as follows:
L. Chrostowski, M. Hochberg, “Silicon Photonics Design”, Cambridge University Press, 2015 (In press)
A. Yariv, P. Yeh, "Photonics: Optical Electronics in Modern Communications", 6th ed.
Lorenzo Pavesi, GĂ©rard Guillot, "Optical Interconnects: The Silicon Approach", Springer Berlin/Heidelberg, 2006, no. 978-3-540-28910-4.
J. Heebner, R. Grover, T. A. Ibrahim, "Optical Microresonators: Theory, Fabrication and Applications", Springer Berlin/Heidelberg, 2008, no. 978-0-387-73068-4.

Course evaluation / assessment
Course evaluation:

  • Project proposal - 5 minute student presentation - Week 2
  • Project design document - Week 6
  • Draft mask layout - Week 10
  • Final mask layout - Week 12
  • Final design report - Week 13

The mask layouts are evaluated using a Design Review Checklist (rubric for mask layout) given to the students. The design documents are evaluated on literature review and background, technical content, design methodology, modeling results, and analysis.

Submission details for the project design document and final design report:

  • 3-8 page report, preferred format 2-column journal style (e.g. IEEE PTL, Optics Letters template), but 1 column ok (e.g., Optics Express) with the following sections
  • Introduction with brief literature review to describe the state-of-the-art in your chosen area of study;
  • Proposed design, with a description of what you propose to fabricate and why, including figure(s) / schematic(s) of your proposed design;
  • Modelling approach, what tools you will be using to model and design;
  • Modelling simulation results, graphs, analysis, discussion
  • Fabrication details, description of any fabrication requirements such as edge coupling, oxide removal, location of your design on the die, layout aspect ratio, etc.; a preliminary list of parameters that you will vary / # of designs, e.g., in a table; and an estimate for size of design
  • Testing, describing how you anticipate testing: edge coupling or vertical grating couplers, single fibres vs. fibre arrays; what equipment will you need and how you will access it (e.g., tunable laser, detector, DC supplies, DC+RF probes, RF network analyzer, pattern generator, eye diagram, bit error rate, etc). Do you require any packaging of your devices to use them in your system-level testing.
  • Sketch of your overall chip layout, indicating how you plan to do your mask layout

Design review checklist (rubric):
Manufacturability

  • Is the design DRC (error) clean? (include explanation and DRCex for the ones that will not be fixed).
  • Has the design been tiled?
  • Will the structure work for the known process variations? (include design with varying parameters)
  • Is the layout considered "safe" from a manufacturability perspective, namely does the layout avoid using a lot of minimum feature sizes?
  • Are there fallback designs or subsets of the "system?

Mask Layout

  • Are all waveguides connected? Are all waveguide paths converted to waveguides with appropriate radius? Is the layout space-efficient?
  • Are the waveguides and optical structures designed in the layout such that they will have low optical loss? (e.g., are other structures far enough away)
  • Are all cell names correct in the .gds file?

Post-processing

  • Does the layout include any necessary alignment markers for subsequent lithography?
  • Are sufficient space allowances included for the release step for suspended structures?
  • Was CMC informed that the chip will need to be post processed?

Off-chip interface (Optical)

  • For edge-coupling waveguides, are the waveguides tapered?
  • Is the probing approach defined (edge coupling or vertical coupling)?
  • Fiber array or single fiber? Is the fiber array or single fiber pitch ok?
  • Are the optical IOs interfering with each other and/or with electrical IOs?
  • Would you be able to visualize the alignment with the microscope (will the fiber or probe block your view or shade parts you need to see for the alignment)?

Off-chip interface (Electrical)

  • Which IOs are RF, which ones are DC? Are their impedance, trace length, etc, ok?
  • Are the IOs being probed only, wirebonded only, both? Are the pads pitch/area ok?

Testing

  • Is the chip testable as a standalone? Does it need to be wirebonded to another device to be able to be measured (e.g. TIA)? Can all signals be probed? (Have structure that can be probed)
  • If DC pads are wirebond and RF pads are probed - can the probe possibly land on bond wires?
  • Are there optical test structures included that can be measured by the automated probe station at UBC?

Packaging:

  • Will it be packaged? Is the IO spacing requirement for packaging met?
  • Does the design follow the available packaging rules (e.g. offsets from edge of the chip, spacing, etc)?

Grading System

  • 20% Project proposal
  • 20% Project design report
  • 20% Draft mask layout
  • 20% Final mask layout
  • 20% Final design report

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