Performance evaluation of wireless networks on chip architectures

TitlePerformance evaluation of wireless networks on chip architectures
Publication TypeConference Paper
Year of Publication2009
AuthorsGanguly, A., K. Chang, P. P. Pande, B. Belzer, and A. Nojeh
Conference NameQuality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design
Pagination350 -355
Date Publishedmar.
Keywordsantennas, energy dissipation, miniaturized on-chip antennas, multihop communication, network-on-chip, network-on-chip architectures, performance evaluation, radio networks, wireless networks, wireless NoC, wireless on-chip networks

The performance benefits of conventional Network-on-Chip (NoC) architectures are limited by the high latency and energy dissipation in long distance multihop communication between embedded cores. To alleviate these problems, wireless on-chip networks are envisioned. Using miniaturized on-chip antennas as an enabling technology, wireless NoCs (WiNoCs) can be designed. In this paper we elaborate on the design methodology and technology requirements for a WiNoC and evaluate its performance. It is demonstrated that a WiNoC outperforms its wireline counterpart in terms of network throughput and latency, and that energy dissipation improves by an order of magnitude.


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