Timing analysis of network on chip architectures for MP-SoC platforms

TitleTiming analysis of network on chip architectures for MP-SoC platforms
Publication TypeJournal Article
Year of Publication2005
AuthorsGrecu, C., P. P. Pande, A. Ivanov, and R. Saleh
JournalMicroelectronics Journal
Volume36
Pagination833–845
ISSN0026-2692
Abstract

Recently, the use of multiprocessor system-on-chip (MP-SoC) platforms has emerged as an important integrated circuit design trend for high-performance computing applications. As the number of reusable intellectual property (IP) blocks on such platforms continues to increase, many have argued that monolithic bus-based interconnect architectures will not be able to support the clock cycle requirements of these leading-edge SoCs. While hierarchical system integration using multiple smaller buses connected through repeaters or bridges offer possible solutions, such approaches tend to be ad hoc in nature, and therefore, lack generality and scalability. Instead, many different forms of network on chip (NoC) architectures have been proposed in the past few years to specifically address this problem. We believe that the NoC approach will ultimately be the preferred communication fabric for next generation designs. To support this conjecture, this paper demonstrates, through detailed circuit design and timing analysis that different proposed NoC architectures to date are guaranteed to achieve the minimum possible clock cycle times in a given CMOS technology, usually specified in normalized units as 10-15 FO4 delays. This is contrasted with the bus-based approach, which may require several design iterations to deliver the same performance when the number of IP blocks connected to the bus exceeds certain limits. (c) 2005 Elsevier Ltd. All rights reserved.

URLhttp://dx.doi.org/10.1016/j.mejo.2005.03.006
DOI10.1016/j.mejo.2005.03.006

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