| Title | Jitter models for the design and test of Gbps-speed serial interconnects |
| Publication Type | Journal Article |
| Year of Publication | 2004 |
| Authors | Ou, N., T. Farahmand, A. Kuo, S. Tabatabaei, and A. Ivanov |
| Journal | Design Test of Computers, IEEE |
| Volume | 21 |
| Pagination | 302 - 313 |
| Date Published | jul. |
| ISSN | 0740-7475 |
| Keywords | bit error rate, communication link performance, error statistics, high-speed interconnects, jitter, jitter model analysis, logic design, logic testing, parallel bus architectures, serial I/O interconnects, signal amplitude noise |
| Abstract | We present a comprehensive analysis of jitter causes and types, and develops accurate jitter models for design and test of high-speed interconnects. The recent deployment of gigabit-per-second (Gbps) serial I/O interconnects aims at overcoming data transfer bottlenecks resulting from the limited ability to increase chip pin counts in parallel bus architectures. The traditional measure of a communication link's performance has been its associated bit error rate (BER), which is the ratio of the number of bits received in error to the total number of bits transmitted. When data rates increase, jitter magnitude and signal amplitude noise must decrease to maintain the same BER. As data rates exceed 1 Gbps, a slight increase in jitter or amplitude noise has a far greater effect on the BER. |
| URL | http://dx.doi.org/10.1109/MDT.2004.34 |
| DOI | 10.1109/MDT.2004.34 |
