Switch-based interconnect architecture for future systems on chip

TitleSwitch-based interconnect architecture for future systems on chip
Publication TypeJournal Article
Year of Publication2003
AuthorsPande, P. P., C. Grecu, A. Ivanov, and R. Saleh
Secondary AuthorsLopez, J. F., J. A. MontielNelson, and D. Pavlidis
JournalVLSI Circuits and Systems
Volume5117
Pagination228–237
ISSN0277-786X
Abstract

System on Chip (SoC) design involves the integration of numerous heterogeneous semiconductor intellectual property (SIP) blocks. The success of this approach depends on the seamless integration of cores like processors, memories, UARTs, etc. Some of the main problems associated with future SoC design arise from non-scalable global wire delays, failure to achieve global synchronization with a single clock, errors due to signal integrity issues, and difficulties associated with non-scalable bus-based functional interconnects. To address these problems, we conjecture the future need and practicality of a paradigm shift in SoC design methodology from a conventional, typically bus-based approach, to, a network-centric approach. In replacement of global wiring, we propose a switch-based on-chip interconnection network to interconnect IP blocks:. One of the challenges in an interconnection network-based SoC is sending data from one IP block to multiple destination IP blocks simultaneously, i.e., multicasting. To achieve multicasting we introduce the concept of a bit-string encoding in the addressing mechanism to communicate among IP blocks. Another major challenge in such network-based SoCs is throughput degradation due to idle physical channels. By introducing the concept of virtual channels in an on-chip interconnection network, the overall throughput of the SoC can be improved. To incorporate the concept of multicasting and virtual channels the silicon area consumed by the switches-will increase, but that can be made to be very small in a billion-transistor SoC.

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