Electrical Engineering Seminar and Special Problems- AMP FOR FPGA
Automated Macro Placement for Field Programmable Gate Arrays
Overview
Macro placement plays an integral role in routability and timing closure in the Field Programmable Gate Array (FPGA) physical design flow. In particular, the discrete and columnated nature of the FPGA device layout presents unique placement constraints on placeable macros (e.g. BRAM’s, DSP’s, etc.). These constraints are challenging for classical optimization approaches, but recent developments in Machine Learning (ML) show promise for overcoming the limitations of classical algorithms. In this course, you will complete a self-directed project in which you will seek ways to leverage ML techniques for solving the FPGA macro placement problem for a commercial FPGA architecture.
Course Format
The course will consist primarily of self-directed project work, guided by academic papers. There will be no set lectures, however students will be expected to meet with the instructor once per week (at a mutually agreeable time). Students will be expected to work individually or in groups to research and develop new ML-based algorithms for FPGA macro placement. These algorithms will be evaluated on a commercial FPGA architecture using commercial FPGA compilation software (in particular, we will use the Xilinx UltraScale+ XCVU3P FPGA and the Xilinx Vivado software suite). This work will be done in the context of a competition organized by AMD that was run as part of the IEEE/ACM MLCAD 2023 workshop (details will be provided to interested students).
The primarily deliverable will be (a) an interim report submitted half-way through the term, (b) a paper-style report that identifies the techniques developed and an evaluation of the solution using available Xilinx benchmarks and software (which will be provided); (c) source code for software that implements the proposed ML algorithm ideas.
Marking
An overall mark will be calculated as follows:
a) Participation in individual meetings with instructor: 25%
Main criterion: leading the discussion with new ideas and insights
b) Interim report submitted half-way through the term: 25%
Main criterion: progress towards final goal, identification and potential resolution of problems identified, plans to complete the algorithm implementation
c) Final report and code submitted at the end of term: 50%
Main criterion: novelty of ideas, quality of results on the Xilinx benchmarks, quality of implementation (eg. code), report quality. Publishable-quality results are expected.
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