Superconducting Quantum Devices for Quantum Computing: Theory, Analysis and Design

Number of credits: 3


Attendance of the QSciTech-QuantumBC-CMC virtual workshop on superconducting circuit and qubits is mandatory.

Because workshop attendance is mandatory, this course is available to first-year and second-year graduate students who start in January or May, but those who start in September (and miss the workshop) will have to wait until year 2 to take thecourse.

Course dates: July to December (this includes the workshop)


Building quantum computers is a great challenge and involves concepts and technology that have similarities and differences with those in classical computers. It involves cryogenic environments and in the currently most advanced approach it relies on superconducting circuits that display quantum effects. The topic of this course is superconducting quantum devices and circuits for quantum computation

This is a 3-credit course broken up two mandatory parts.

Part 1: The first part of the course, which is mandatory, is a workshop in July where students learn the theory of how the devices behave, how to analyze superconducting devices and circuits, and how to design devices and circuits that arecompatible with foundry-based fabrication.

PART 2: The second part of the course, which is mandatory, is a course project carried out from September to December, where the deliverable is a midterm report and final report on the design, analysis, and fabrication of superconducting circuitsfor quantum computing.

Part 1 (2021): July 19 to 30: Attendance of the QScitech-QuantumBC-CMC virtual workshop on superconducting circuit and qubits is mandatory. Part 2 (2021): September toDecember

Learning objectives

The learning objectives for the course are:

  1. Be able to use models to predict the performance and behaviour of superconducting devices and circuits
  2. Be able to do physical design of a superconducting devices and circuits
  3. Be able to compare foundry processes to see their impact on the performance of devices.
  • Translate of the physical design to a foundry compatible process

Evaluation is based on one presentation of the project proposal and on two reports. The first report is on the analysis anddevice design. The second report is a final design report.


Lecture format: A total of fifteen (15) 90-minute lectures during the summer workshop “superconducting circuits and qubits” delivered by worldwide experts in the field from academia (UBC, UVic, Sherbrooke) and industry (D-Wave and IBM).

Lecture contents:

  1. Theory of applied superconductivity: Penetration depth, Josephson effect, RF and DC SQUIDS
  2. Theory of superconducting devices as quantized circuits: canonical quantization, the

Josephson Junction as a nonlinear device

  • Theory of circuit extraction and distributed circuit design: transmission lines, resonators, and filters.
  • Introduction to design tools: IBM Metal, Ansys
  • Theory of two-level quantum systems, harmonic oscillators, circuit elements, quantizing circuits.
  • Design tutorial: coplanar waveguide resonator and lumped element resonators for qubit


  • Theory: readout of superconducting circuits, superconducting analog to digital converters
  • Design tutorial : RF-SQUID qubit and readout circuitry
  • Theory: Single-Flux Quantum Logic
  • Tutorial: Foundry manufacturing process description and process design kit
  • Tutorial: Experimental measurement : cryogenics, low-frequency measurement, signal­ to-noise ratio, 1/f noise.
  • Tutorial: Experimental measurement : microwave scattering parameters, measurement bandwidth, signal-to-noiseratio, thermal noise, shot noise.
  • Tutorial: Lay out: chip dimensions, design rules, layout generation
  • Tutorial: Design for test.

Course evaluation/assessment

Course timing:

  • Deliverable: Project proposal -5 minute student presentation – Week 2
  • Deliverable: Project design report Rl -Week 7
  • Draft mask layout – Week 10
  • Final mask layout – Week 12
  • Deliverable: Final design report R2- Week 13

Details of reports

The project design report (Rl) and final design report (R2) have the following sections and are 4 pages and 8 pages,respectively, in 2-column format

  • Rl: Introduction: What is the problem, how has it been tackled before, what are the remaining problems?
  • Rl: Proposed design: What you plan to design and why? Figures and schematics of the proposed design
  • Rl: Methodology: tools you plan to use to predict device and circuit behaviour
  • Rl: Results: Output of the methodology once applied to your design.
  • Rl/R2: Fabrication details: description of the fabricated design
  • Rl/R2: Test plan: how you anticipate testing the circuit
  • Rl/R2: Appendix: overall chip layout

Grading system

  • 10% Project proposal
  • 50% Project design report
  • 40% Final design report

More Information

UBC Course Page